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As semiconductor technology keeps scaling down, leakage power grows significantly due to the reduction in threshold voltage, channel length, and gate oxide thickness. As the junction temperature increases in nano-scale devices, leakage power increases drastically. This phenomenon motivates the processor and package designers to take into account thermal effects due to the large leakage power for highly reliable design of high-performance systems. In this paper, an analytical methodology for estimating the junction temperature and initial temperature range was provided to avoid diverging junction temperature status in nano-scale devices. For this purpose, junction temperature decision (JTD) map and initial temperature limit (ITL) map was newly introduced.