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A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation

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2 Author(s)
Yoshizawa, A. ; Dept. of Electr. Eng., Columbia Univ., New York, NY ; Tsividis, Y.

A dynamic biasing scheme that reduces the average DC power of channel-select filters in wireless receivers is presented. A blocker detection technique makes it possible to automatically adjust the power dissipation depending on the absence of presence of blockers, with low overhead in power consumption and circuit complexity. The scheme achieves a fast ramp-up, avoiding diminution of the desired signal response that could otherwise be caused by abruptly appearing large blockers. To ensure the stability of the dynamically biased class-AB opamp employed, a cascode Miller/feedforward compensation technique is used. A fifth-order Butterworth low-pass filter with adaptive IIP3 and adaptive power dissipation is demonstrated, with a test chip implemented in a 0.18-mum CMOS process with a 1.8-V supply. The filter quiescent current is 1.2 mA in the absence of blockers, with a -5 dBV out-of-channel IIP3. The current increases to 2.7 mA, with the IIP3 of +20 dBV, when the blocker level rises to -13 dBV

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Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 5 )