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Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention

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4 Author(s)
Sarkar, J. ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX ; Dey, S. ; Shahrjerdi, D. ; Banerjee, Sanjay K.

We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F 2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 degC. The cell shows a large memory window of ~1 V and endurance of more than 105 cycles

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 5 )