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This paper describes the design and architecture of a novel VLSI gate array in CMOS technology and its application for a 3-bit error checking and correcting (ECC) unit. The cell rows of the master are arranged without intermediate channels for routing (``sea of gates''). This scheme can be utilized to build large macro cells and functional blocks like data paths or systolic array cells which are very area consuming to realize in conventional gate arrays. In addition, special pull-up/pull-down cells are included on the chip which can be used for data buses and timing circuits. The technology used is an advanced p-well CMOS process with 1.8-Âµm geometric channel lengths and a two-layer metallization. There are 260 programmable pads for input/output functions and 20 additional power pads (280 pads in total). Depending on the logic, circuits with up to 25 000 gates can be realized with this device.