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A Small-Scale Distributed Microprocessor System Using Shared Memory Technique

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2 Author(s)
Papasratorn, B. ; The Department of Electrical Engineering, Chulalongkorn University, Bangkok 10500, Thailand. ; Prapinmongkolkarn, P.

A simple technique for arranging interprocessor communication through a shared random access memory (RAM) in a small-scale distributed microprocessor system is presented. An arbiter which employs a simple hardware and requires no external clock is proposed. The arbiter consists of a controller and a scanner. The controller receives a shared memory request from a microprocessor and sends a GRANT or WAIT signal back to the microprocessor according to a command from the scanner. The scanner schedules the shared memory accessing for each microprocessor. The technique can be used for interprocessor communication at a rate of less than 87 kbytes/s with 4 Z-80 microprocessors working at a 2-MHz clock signal. The microprocessors in the system need not be identical, but are required to have a WAIT state and a FETCH state indicator. The system can be increased up to 6 microprocessors and is good for a small-to-medium scale real-time control application. A front-end communication system using the proposed system is also presented as an application.

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Industrial Electronics, IEEE Transactions on  (Volume:IE-32 ,  Issue: 2 )