FPGA Implementation of Parallel Pipelined Multiplier Less FFT Architecture Based System-On-Chip Design Targetting Multimedia Applications

This paper proposes a novel SoC design based on parallel-pipelined multiplier less FFT architecture targeting multimedia applications. The proposed architecture has the advantages of less complexity, more speed, high throughput, and low cost and high power efficiency. This demands use of system level design methodologies from behavior level to fabrication level like software and hardware co-design, use of intellectual properties, reusability from netlist, co-design and verification. This architecture is compatible for both video processing and audio processing including video compression. This paper deals with various dimensions of the designing and implementation of a SoC using reuse concept