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A Method to Evaluate Power Domain Problems in SoC

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2 Author(s)
Cetin, J. ; Cypress Semicond., San Diego, CA ; Balasinski, Artur

Noise of the power supply voltage can disturb SoC operation by modulating signal frequency of its individual blocks related to their drive current. This disturbance typically results from the complex functions of the SoC combined with their low pin count and current routing not supporting the power demand in the different sections of the die. The pin count, minimized to help take advantage of die area reduction due to technology shrinks calls for fewer power domains resulting in an increase of the current per domain. This, combined with the larger resistance and inductance of the wiring to the target location on the die, due to the increased functionality, gives rise to the DC (IR) and transient (L di/dt) voltage droop, the severity of which increases with every product generation. At the same time, the "hot spots" of power distribution are difficult to identify due to the distributed nature of the power supply current and voltage. In this work, a novel approach to evaluate power domain problems in SoC was proposed, based on a multi-level analysis of the distribution of total die power to help determine what design tools should be engaged and at which complexity level. Starting from the initial criterion i.e., silicon verification, it was recommended that power domain analysis is not required for the domains proven on silicon. It was then shown that the analysis at a rudimentary level is sufficient if adequate static and dynamic power safety margins can be proven. In such analysis, one may need to perform a relatively simple block level assessment to ensure product functionality in a standard package, depending on the line inductance and operating frequency. For the high die current levels, one would be required to use advanced design tools to resolve problems within every current node and voltage loop, and the preliminary analysis can help define the critical domains. How the noise of the power supply system should be considered throughout the design review process- was shown

Published in:

System-on-Chip for Real-Time Applications, The 6th International Workshop on

Date of Conference:

Dec. 2006