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Current-Mode Phase-Locked Loops— A New Architecture

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2 Author(s)
Dominic DiClemente ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont. ; Fei Yuan

This brief introduces current-mode phase-locked loops (PLLs). The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing their RC loop filter with a RL loop filter, eliminating the need for large on-chip capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and tunable inductance and small silicon area. Both types I and II current-mode PLLs are introduced. Implemented in TSMC 0.18-mum CMOS technology, the simulation results of a 3-GHz current-mode PLL demonstrate that the PLL has the lock time 50 ns, silicon area 2800 mum2, dc power consumption 12.2 mW, and phase noise of -84.5 dBc at 1-MHz frequency offset and the maximum -74 dBc reference spurs

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:54 ,  Issue: 4 )