Referenced Items are not available for this document.
Most existing techniques for reconfigurable processors focus on the computation model. This paper focuses on increasing the granularity of configurable units without compromising flexibility. This is carried out by matching the granularity to the degree-of-freedom processing in most wireless systems. A design flow that accelerates the exploration of tradeoffs among various architectures for the configurable unit is discussed. A prototype processor is implemented using the Intel 0.13-mum CMOS standard cell library. The estimated energy efficiency is in the same order as dedicated hardware implementations
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:15
,
Issue:
3
)
Date of Publication: March 2007
- Page(s):
- 319 - 327
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 9416867
- Digital Object Identifier :
- 10.1109/TVLSI.2007.893619
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 16 April 2007
- Issue Date :
- March 2007
- Sponsored by :
- IEEE Circuits and Systems Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
