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A New Surface Potential Based Poly-Si TFT Model for Circuit Simulation

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10 Author(s)
H. Tsuji ; Division of Electrical, Electronic and Information Engineering, Osaka University, Suita, Osaka 565-0871, Japan. Tel: +81-6-6879-7731, Fax: +81-6-6879-7792, E-mail: tsuji@si.eei.eng.osaka-u.ac.jp ; T. Kuzuoka ; Y. Kishida ; Y. Shimizu
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A new surface potential based poly-Si TFT model for circuit simulation was developed, accounting for the influence of both deep and tail states across the band gap. The model describes the drain current for all regions of operation using the unified equation. Calculations using the drain current model produce results that are in good agreement with the measured I-V characteristics of poly-Si TFTs

Published in:

2006 International Electron Devices Meeting

Date of Conference:

11-13 Dec. 2006