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Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices

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35 Author(s)
Han, J.P. ; Infineon Technol., Munich ; Utomo, H. ; Teo, L.W. ; Rovedo, N.
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We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics such as silicide and junction characteristics were not degraded

Published in:

Electron Devices Meeting, 2006. IEDM '06. International

Date of Conference:

11-13 Dec. 2006