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A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

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57 Author(s)
H. Nii ; System LSI Division 1, Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 210-2582, Japan, Phone: +81-45-770-3498, FAX: +81-45-770-3194. E-mail: ; T. Sanuki ; Y. Okayama ; K. Ota
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We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance of Ion=1100muA/mum for nFET and Ion=700muA/mum for pFET at Ioff=100nA/mum. Also, we achieved excellent BEOL reliability and manufacturability by implementing hybrid dual-damascene (DD) structure with porous low-k film (keff=2.7)

Published in:

2006 International Electron Devices Meeting

Date of Conference:

11-13 Dec. 2006