We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (VT =0.33V), low equivalent oxide thickness (EOT=0.91nm) (Tinv =1.3nm) and 83% SiO2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET VT tuning 2) HfO2:SiO2 alloy ratio with 10% SiO2 suppressing crystallization up to 1070degC, 3) interlayer SiO2 (IL) to reduced bias temperature instability (BTI) and 4) plasma nitridation (N*)/post nitridation anneal (PNA) sequence for EOT scaling. This work advances high-k/band edge metal gate (MG) efforts by showing scalability of HfLaSiON to EOT=0.91nm without mobility or BTI tradeoff, while matching the VT of a SiO2/n-PolySi control
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Electron Devices Meeting, 2006. IEDM '06. International
Date of Conference: 11-13 Dec. 2006