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Full wafer integration of NEMS on CMOS by nanostencil lithography

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9 Author(s)
Arcamone, J. ; Spain Microsyst. Lab., Ecole Polytechnique Federale de Lausanne ; van den Boogaart, M.A.F. ; Serra-Graells, F. ; Hansen, S.
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Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nano-devices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around 1.5 MHz were measured in air and vacuum and tuned by applying dc voltages of 10V and 1V respectively

Published in:

Electron Devices Meeting, 2006. IEDM '06. International

Date of Conference:

11-13 Dec. 2006