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Novel Anisotropic Strain Engineering on (110)-Surface SOI CMOS Devices using Combination of Local/Global Strain Techniques

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8 Author(s)
T. Mizuno ; MIRAI-AIST, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, Japan 212-8582; Kanagawa University, 2946, Tsuchiya, Hiratsuka 259-1293, Japan mizuno@info.kanagawa-u.ac.jp ; T. Irisawa ; N. Hirashita ; Y. Moriyama
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We have experimentally studied a new (HO)-surface anisotropic strained-SOI, using the combination of partially-strained global SGOI substrates and the uniaxial relaxation effects in the narrow SiGe layers. We have demonstrated much larger drain current Id enhancement of (110) anisotropic strained-SOIs against (HO)-SOIs than that of biaxial-strained ones. The optimum (110) strained-SOI CMOS consists of the biaxial strained n-MOS and the anisotropic strained p-MOS for the larger drain currents and the simple fabrication processes

Published in:

2006 International Electron Devices Meeting

Date of Conference:

11-13 Dec. 2006