Cart (Loading....) | Create Account
Close category search window

Novel Anisotropic Strain Engineering on (110)-Surface SOI CMOS Devices using Combination of Local/Global Strain Techniques

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

We have experimentally studied a new (HO)-surface anisotropic strained-SOI, using the combination of partially-strained global SGOI substrates and the uniaxial relaxation effects in the narrow SiGe layers. We have demonstrated much larger drain current Id enhancement of (110) anisotropic strained-SOIs against (HO)-SOIs than that of biaxial-strained ones. The optimum (110) strained-SOI CMOS consists of the biaxial strained n-MOS and the anisotropic strained p-MOS for the larger drain currents and the simple fabrication processes

Published in:

Electron Devices Meeting, 2006. IEDM '06. International

Date of Conference:

11-13 Dec. 2006

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.