By Topic

Real-Time Stereo Vision Processing System in a FPGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Cuadrado, C. ; Dept. of Electron. & Telecommun., Basque Country Univ., Bilbao ; Zuloaga, A. ; Martin, J.L. ; Lazaro, J.
more authors

This paper describes a reconfigurable digital architecture to compute dense disparity maps at video-rate for stereo vision. The processor architecture is described in synthetizable VHDL and, by means of the reconfigurability, the hardware requirements are optimized for different image resolutions and matching scenarios. The configurable description of a stereo processor provides the entity to design stereo matching systems, implementing by incremental design multi-baseline or multi-scale stereo vision algorithms. We show the results of the synthesis and its implementation cost in logic elements and time delays. The synthesis results have been implemented in a practical prototype

Published in:

IEEE Industrial Electronics, IECON 2006 - 32nd Annual Conference on

Date of Conference:

6-10 Nov. 2006