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Cycle-Accurate Performance Evaluation of Parallel Jpeg2000 on a Multiprocessor System-on-Chip Platform

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2 Author(s)
Smorfa, S. ; Rome Univ. ; Olivieri, N.

Jepg2000 is a high-performance and flexible image compression algorithm whose practical integration within commercial products presently suffers from its labor-intensive and resource-demanding computational core. We investigated a multiprocessor implementation of Jpeg2000 encoder to demonstrate that a proper task allocation and communication architecture allows significant performance improvement. We devised a multiprocessor SoC architecture based on STMicroelectronics LX-ST230 VLIW processor nodes and set up an all-inclusive simulation environment to assess its overall performance. On average, we obtained a nearly Amdahl-optimal speedup with respect to the single processor solution, for color image compression

Published in:

IEEE Industrial Electronics, IECON 2006 - 32nd Annual Conference on

Date of Conference:

6-10 Nov. 2006