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3D on-chip networking technology based on post-silicon devices for future networks-on-chip

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4 Author(s)
Fujita, Shinobu ; Frontier Res. Lab., Toshiba Corp., Kawasaki ; Nomura, K. ; Abe, K. ; Lee, T.H.

We propose a 3D architecture using post-silicon devices, such as nano-mechanical electrical switches, carbon nanotube FETs, and nanowire FETs, for future networks-on-chip (NoC). Based on such a new 3D architecture, extremely high bandwidth with very low latency can be realized. These promising features are very useful for future NoCs

Published in:

Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on

Date of Conference:

Sept. 2006

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