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A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

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3 Author(s)
Miro Panades, I. ; STMicroelcctronics, Grenoble ; Greiner, A. ; Sheibanyrad, A.

The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture. DSPIN is a scalable packet switching micro-network dedicated to GALS (globally asynchronous, locally synchronous) clustered, multi-processors, systems on chip. The DSPIN architecture has a very small footprint and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications

Published in:

Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on

Date of Conference:

Sept. 2006