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On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture

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3 Author(s)
Jun Ho Bahn ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Irvine, CA ; Seung Eun Lee ; Bagherzadeh, N.

In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algorithm even if basic network problems such as deadlock and livelock, are considered. We develop a new packet definition to support different requirements in an MIMD message passing architecture and also verify its efficiency by comparing simulation results with various routing algorithms. Major contributions of this paper are the design of network-on-chip (NoC) architecture adopting a minimal adaptive routing algorithm with competitive performance and feasible design complexity, thus satisfying all the stated design goals. The proposed adaptive routing algorithm and NoC architecture offer nearly optimal performance. This can be shown by comparing with the near-optimal worst-case throughput routing algorithm for 2D-mesh networks. By providing a uniform way of constructing such network architecture, its scalability can be easily accomplished. Moreover, this network architecture can be applied to different SoC developments

Published in:

Information Technology, 2007. ITNG '07. Fourth International Conference on

Date of Conference:

2-4 April 2007

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