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NXG06-3: The Central-stage Buffered Clos-Network to Emulate an OQ Switch

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3 Author(s)
Feng Wang ; Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., Kowloon ; Wenqi Zhu ; Hamdi, M.

In this paper, we propose a highly scalable packet switch that is based on a multi-stage multi-layer architecture made up of many modest size switches. This new architecture resembles the famous Clos-network studied in circuit switching systems except that it has distributed shared memories in the central stage. We call it central-stage buffered Clos-network (CBC). We first analyze the memory requirements for the CBC to emulate an output-queued (OQ) switch since OQ switches are generally regarded as having the optimal delay-throughput performance. Then we design an efficient packet-scheduling algorithm for the CBC to emulate an FCFS OQ switch. We show two distinguished features of this algorithm. First, it converges to the maximum matching faster than any other scheduling algorithms using the same paradigm. Secondly, the performance of the algorithm is independent of any arriving traffic pattern, which is not seen in other scheduling algorithms, such as iSLIP, DRRM and so on...

Published in:

Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE

Date of Conference:

Nov. 27 2006-Dec. 1 2006