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NXG06-2: A Practical Switch-Memory-Switch Architecture Emulating PIFO OQ

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5 Author(s)
Nan Hua ; Dept. of Electron. Eng., Tsinghua Univ., Beijing ; Yang Xu ; Peng Wang ; Depeng Jin
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Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The Switch-Memory-Switch (SMS) router, also called Distributed Shared Memory (DSM) Switch, provides a possible way towards practically emulating OQ in backbone switches. However, the architectures and algorithms for SMS switches ever proposed are either unpractical or only supporting First-Come-First-Serve (FCFS) scheduling policy, which cannot support QoS and is unfair for light traffic flow. Our improved SMS architecture and algorithm aim at emulating Push-In-First-Out (PIFO) OQ. We employ a randomly-dispatching first stage and resolve memory access conflictions on the second stage of the switch through a probabilistic matching method, at the cost of fixed delay and sufficiently low cell loss probability (PCLP). The relative fixed delay of our algorithms for an NXN switch is composed of two parts: N and (-3/2log2PCLP), which result from the pipelined scheduling process and probabilistic method, respectively. Moreover, both the total memory and fabric bandwidth of our architecture implemented on crossbar could be lowered to only 2NR, where R is line rate, counting read and write separately.

Published in:

Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE

Date of Conference:

Nov. 27 2006-Dec. 1 2006

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