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GEN03-6: Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation

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5 Author(s)
Zhengya Zhang ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA ; Dolecek, L. ; Nikolic, B. ; Anantharam, V.
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Several high performance LDPC codes have parity-check matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any structured LDPC code in this large family to a hardware emulation platform. A peak throughput of 240 Mb/s is achieved in decoding the (2048,1723) Reed-Solomon based LDPC (RS-LDPC) code. Experiments in the low bit error rate (BER) region provide statistics of the error traces, which are used to investigate the causes of the error floor. In a low precision implementation, the error floors are dominated by the fixed-point decoding effects, whereas in a higher precision implementation the errors are attributed to special configurations within the code, whose effect is exacerbated in a fixed-point decoder. This new characterization leads to an improved decoding strategy and higher performance.

Published in:

Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE

Date of Conference:

Nov. 27 2006-Dec. 1 2006

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