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Design of multioutput CMOS combinational logic circuits for robust testability

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1 Author(s)
Kundu, S. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

The author proposes a testable design for multioutput functions using parity gates that always produces a realization with robust tests. The use of parity gates allows more logic sharing among various outputs than would have been possible otherwise. The solution presented here has the ability to accommodate any fan-in restriction and grow in number of levels. The new design is well suited for multioutput circuits

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:8 ,  Issue: 11 )