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Cross Layer Error Exploitation for Aggressive Voltage Scaling

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4 Author(s)

This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3 GPP WCDMA modem

Published in:

Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on

Date of Conference:

26-28 March 2007

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