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Scalable PEEC-SPICE modelling for EMI analysis of power electronic packages and subsystems

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2 Author(s)
Didier Cottet ; ABB Switzerland Ltd., Baden-Dattwil ; Mikko Paakkinen

In this paper we present a method for scaling component and subsystem models for electromagnetic interference (EMI) analysis of power electronic systems using a SPICE simulator. The modelling is done using the partial element equivalent circuit (PEEC) method for extracting the component's parasitic impedance matrices and to create SPICE compatible component sub-circuits. The scaling method consists of separating system components with negligible cross-coupling, combining component pins for reducing the impedance matrix sizes, and scaling the semiconductor device models to combine paralleled chips into one model. The method allows selective scaling and therefore, finding the right balance between required level of detail and computing effort. Comparisons to measurements have shown that the models are very accurate, especially at turn-off and on-state

Published in:

2006 8th Electronics Packaging Technology Conference

Date of Conference:

6-8 Dec. 2006