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A number of three dimensional packaging solutions have emerged in recent years. Embedding active components in the build-up layers of a printed circuit board is a cost-effective technology, providing a high degree of integration for future packaging requirements. Since this technology offers clear advantages for high-speed applications, a high-frequency characterization is essential. This paper studies the influence of embedded chips on high-speed interconnects running on top. A similar geometry found in integrated circuits is used as a start for the research. Investigation of this metal-insulator-semiconductor transmission line reveals three propagating modes, depending on frequency and silicon conductivity: a dielectric mode, the skin-effect mode and the slow-wave mode. A mode analysis of the parallel-plate approximation is used to formulate detailed expressions describing the frequency dependent behavior of the real and imaginary part of the effective dielectric constant. 3D electromagnetic simulations confirm that this model gives a good description of the behavior of embedded dies, but needs some adjustments to accurately predict the results. The parameters extracted from the measurement show a good correspondence to the model as far as the real part of the dielectric constant is concerned. Due to the limitations of the available test structures, an accurate quantitative analysis of the losses is not possible; however the overall behavior matches with the model. The specific geometry of substrates with embedded components requires adaptations to the formulae predicted by the parallel-plate approach. Especially the presence of a die bonding adhesive layer and the high track thickness needs to be taken into account. This paper shows that the MIS model can act as a good starting point for an in depth characterization of microstrips running on top of embedded components.