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Application of finite element analysis on flip chip ball grid array package with 65nm Cu/low-κ device

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3 Author(s)
Yeo, A. ; Infineon Technol. Asia Pacific Pte Ltd., Singapore ; Tan Ai Min ; Lee, C.

This paper demonstrates the application of finite element method in understanding the Cu/low-κ structure deformation mechanism during flip chip packaging. Four different modeling methods, detailed global model, global-local model, global-local model with homogenization procedure and sub-structure model were employed. In spite of the different modeling approaches, all models predicted the same maximum stress locations at the die-underfill interface and in the Cu/low-κ device after flip chip packaging. Both global-local model with the homogenization step and Sub-structure model were preferred in terms of modeling efficiency. From the global-local model analysis, the thermo-mechanical stress induced by packaging load from the global effect and the local thermal mismatch from the Cu/low-κ interconnect structure was comparable. Generally, underfills with lower CTE, higher E-modulus and lower Tcure yielded a lower stress in the Cu/low-κ interconnect structure after the flip chip package assembly.

Published in:

Electronics Packaging Technology Conference, 2006. EPTC '06. 8th

Date of Conference:

6-8 Dec. 2006