Implementing a Vector RLS Smart Antenna Beamformer Using Xilinx System Generator

The vector RLS (VRLS) beamformer is a promising algorithm for weight vector adjustment in many smart antenna applications because of its linear computational complexity and high convergence rate of SNIR to the optimum solution. The fixed-point numerical performance of the VRLS beamformer is discussed in this paper. The core VRLS beamformer block is being developed and its basic components such as the complex multiplier, the complex vector multiplier and the complex elements multiplier were designed using Xilinx System Generator. The ModelSim tools that includes a complete very high-speed integrated circuit hardware description language (VHDL) simulation and debugging environment was used to stitch the basic components together. The running speed of the core block for four elements antenna array was obtained for the test input data. Some optimizations of the hardware implementation based on FPGA are proposed