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In this work we present a new AES-CBC crypto-core for System-on-Programmable-Devices. The core architecture can fit three different open-source AES block implementations. Each one can be instantiated in order to obtain cores with different area-speed trade off, which eases and optimizes the secure communications implementation in industrial embedded systems. The implementation results for the different versions are presented and evaluated.
Date of Conference: 27-30 Nov. 2006