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A Low Multiplier and Multiplication Costs 256-point FFT Implementation with Simplified Radix-24 SDF Architecture

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3 Author(s)
Chih-Peng Fan ; Dept. of Electr. Eng., National Chung Hsing Univ., Tai-chung ; Mau-Shih Lee ; Guo-An Su

In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple. The hardware requirement of the proposed FFT architecture only needs 1 complex multiplier and 56 complex adders for supporting 256-point computations. The computation complexity of multiplications and the hardware complexity of the proposed FFT architecture need less complexity than both complexities of the previous FFT structures in 256-point FFT applications. In hardware verifications, the output throughput rate of our FFT design processes up to 35.5M samples/sec with Xilinx Virtex2 1500 FPGA, and it processes up to 51.5M samples/sec with UMC 0.18mum standard cell technology. The throughput rate of this implementation is suitable for WiMAX 802.16a application, whose maximum sample rate is 32MHz

Published in:

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Date of Conference:

4-7 Dec. 2006