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Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic

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4 Author(s)
Gopal Paul ; Dept. of Computer Science and Engg., Indian Institute of Technology - Kharagpur, WB - 721302, India. gpaulcal@yahoo.com ; Sambhu N. Pradhan ; Ajit Pal ; Bhargab B. Bhattacharya

Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based synthesis technique using dual rail static differential cascode voltage switch with pass gate (DCVSPG) logic. The method yields around 22% reduction in number of MUX cells. Simulation result using SPICE on 180 nm technology with 1.5 volts supply shows, on an average, 65% reduction in power consumption for frequency ranging up to 1 GHz compared to the result with static CMOS logic. It is envisaged that the proposed approach is useful in realizing low-power circuits

Published in:

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Date of Conference:

4-7 Dec. 2006