An Automatic Cache Generator Based on Content-Addressable Memory

The paper presents a cache generator using content-addressable memory (CAM) array for fast tag comparison and low power consideration. The generator produces a hard IP for storage arrays and a soft IP for controller. The hard IP is composed of CAM array and SRAM array, both automatically generated using the developed CAM generator and SRAM generator. The soft IP is mainly the cache controller with parameterized modules to meet the user's specification on different cache architectures (direct-map, set-associative) and write policies (write-through, write-back), write-miss options (write-allocate, no-write-allocate). The cache generator also produces all the necessary models and files required in the standard cell-based design flow for co-simulation with other ASIC designs