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Pipelined Parallel Architectures for High Throughput Turbo Decoding

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2 Author(s)
Xizhong Lou ; Coll. of Inf. Eng., China Jiliang Univ., Hangzhou ; Yanmin Chen

A new pipelined parallel architecture for turbo decoding is presented. It runs at nearly four times the speed of the traditional architecture with tolerable hardware resource increasing. The bottleneck in turbo decoder is the add-compare-select-offset (ACSO) unit used in forward and backward recursive state metrics (FRSM, BRSM) calculation. In the new architecture the critical path in ACSO unit is divided into four shorter evenly parts by inserting four register vectors, which improves the working frequency of the turbo decoder. And the sliding window architecture is modified to make use of the new ACSO unit. At the same time, the received symbol sequence is divided into four evenly pieces, that are fed into the same ACSO unit one after another to form the pipeline. Then the speed of turbo decoder will be approximately four times as the old one

Published in:

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Date of Conference:

4-7 Dec. 2006