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A 0.18μm CMOS Receiver with Decision-feedback Equalization for Backplane Applications

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3 Author(s)
Miao Li ; Department of Electronics, Carleton University, Ottawa, ON Canada. mili@doe.carleton.ca ; Tad Kwasniewski ; Shoujun Wang

Decision-feedback equalization (DFE) is explored to reduce inter-symbol interference (ISI) and crosstalks in highspeed backplane applications. In the design of clock and data recovery (CDR) circuit, embedding DFE within phase and frequency detector (PFD) enhances to recover data inherently from distorted input signals and facilitates to provide DFE with recovered clock. With PRBS15 data signaling at 5-Gb/s over 34" FR4 backplane, SPECTRE simulation in 0.18-μm CMOS process has shown the design feasibility

Published in:

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Date of Conference:

4-7 Dec. 2006