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Subword Parallel Architecture for Connected Component Labeling and Morphological Operations

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2 Author(s)
Wei-Kai Chan ; Media IC and System Lab, Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, BL-421, 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan. archer@media.ee.ntu.edu.tw ; Shao-Yi Chien

Connected component labeling (CCL) and morphological operations are two widely used techniques in vision automation and pattern analysis. There is several hardware architectures proposed for these two operations in literature. However, most of them have two drawbacks: hardware cost inefficient and poor bus bandwidth utilization. This paper applies subword level parallelism on the design of hardware architectures for these two techniques. The implementation result shows that the proposed subword parallel architecture can save 48% of hardware cost in terms of gate count for morphological operations and save even more than 99% of hardware cost in terms of gate count for CCL when both compared with other works, but the programmability and processing speed are remained as well as them. Besides, this architecture is also better in bus bandwidth utilization when compared with other works

Published in:

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Date of Conference:

4-7 Dec. 2006