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Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform

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2 Author(s)
Mohanty, B.K. ; Dept. of Electron. & Commun. Eng., Jaypee Inst. of Eng. & Technol. Raghogarh, Madhya Pradesh ; Meher, P.K.

In this paper, we present a fully pipelined and modular array architecture for reduced-latency high-speed implementation of discrete wavelet transform (DWT). The efficiency of the structure is improved in the proposed design by implementing the computation for the first level decomposition by pyramid algorithm and higher level decomposition by recursive pyramid algorithm in the same processing modules. The proposed structure can support an input data sequence of sampling rate (2/Tm ), and performs N-point DWT in N/2 computational cycles. It has the same hardware utilization efficiency and involves the same number of multipliers/adders as that of the corresponding existing structure, but it needs half the number of registers to store the filter coefficients, and 16.6% less computation time compared with that of the other. Unlike the existing high-speed architecture, the computational core of the proposed structure is comprised of a regular and locally connected systolic array of identical processing modules

Published in:

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Date of Conference:

4-7 Dec. 2006

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