By Topic

Design of a Low Power Architecture for CABAC Encoder in H.264

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chien-Chung Kuo ; Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 701, Republic of China. ; Sheau-Fang Lei

In this paper, we propose a low power architecture for the implementation of context based adaptive binary arithmetic coding (CABAC) system in H.264. CABAC needs to have the accurate probability estimations for most probable symbol (MPS) to enhance higher compression ratio. This data compression efficiency can be implicitly achieved by iteratively updating probability models stored in the embedded memory for hardware design. Therefore the design of the memory hierarchy and the suitable architecture is an important issue so that the power consumption can be kept low caused by memory accesses for iteratively executing arithmetic coding operations. To address the low power consideration for designing a CABAC encoder, we propose the architecture by using variable length tag cache memory scheme and pipeline structure. The simulation results show that our proposed architecture can achieve 50% power consumption saving, and throughput can be higher than 200Mbps

Published in:

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

Date of Conference:

4-7 Dec. 2006