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In the context of RF and high-speed circuits, Systems On Chip with Analog and Mixed Signals (SOC-AMS), interconnect has becoming a dominant factor in determining circuit performance and reliability in deep submicron designs. Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. Coupling noise between adjacent interconnects can also cause catastrophic effects on the logical functionality and long-term reliability of a VLSI circuit. With these trends, the electrical phenomena that have to be investigated are governed by the electromagnetic theory. However, it's impossible to proceed to a complete SOC - AMS analysis with a full wave electromagnetic numerical tool, due to the large scale integration. As interconnects are typically of very large size and high-order, model-order reduction becomes necessary for efficient SOC modeling, simulation, design and optimization. In this communication, a new method based on numerical inversion of Laplace transform and on a discrete model-reduction technique is presented for simulating peak crosstalk noise problems found in high speed digital circuits and SOC-AMS. The method, particularly efficient and easy to be implemented in a program, is useful for an electromagnetic simulation of a complete system.