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Design Methodology for Global Resonant H-Tree Clock Distribution Networks

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2 Author(s)
Rosenfeld, J. ; Dept. of Electr. & Comput. Eng., Rochester Univ., NY ; Friedman, E.G.

Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described, supporting the design of low power, skew, and jitter resonant H-tree clock distribution networks. Excellent agreement is shown between the proposed model and SpectraS simulations. A case study is presented that demonstrates the design of a two-level resonant H-tree network, distributing a 5-GHz clock signal in a 0.18-mum CMOS technology. This example exhibits an 84% decrease in power dissipation as compared to a standard H-tree clock distribution network. The design methodology enables tradeoffs among design variables to be examined, such as the operating frequency, the size of the on-chip inductors and capacitors, the output resistance of the driving buffer, and the interconnect width. A sensitivity analysis of resonant H-tree clock distribution networks is also provided. The effect of the driving buffer output resistance, on-chip inductor and capacitor size, and signal and shielding transmission line width and spacing on the output voltage swing and power consumption is described

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:15 ,  Issue: 2 )