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Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs

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3 Author(s)
Jyh-Ting Lai ; Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei ; An-Yeu Wu ; Chien-Hsiung Lee

Traditional approaches of automatic gain control (AGC) involve estimating the average power or the peak amplitude over an extended time period, which results in high hardware complexity and a long processing time. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference. In this paper, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the AGC circuitry comprises only one-tenth of the area of a traditional AGC. In addition, the total convergence time of the proposed Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-mum cell libraries

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:15 ,  Issue: 2 )