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Access Queues for Multi-Bank Register Files Enabling Enhanced Performance of Highly Parallel Processors

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5 Author(s)
Mukuda, Y. ; Res. Center for Nanodevices & Syst., Hiroshima Univ. ; Aoyama, K. ; Johguchi, K. ; Mattausch, H.J.
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The proposed register access queues are used as part of a scheduler which avoids possible access conflicts for a multi-bank register file in the highly parallelized processor. From the design and implementation in 180 nm CMOS technology, a multi-bank register file with the access queue realizes 65 % smaller area and 64 % higher clock frequency when compared with a conventional multi-port-cell register file. Since the cycle-based execution performance of the processor remains practically unchanged, the higher clock frequency translates directly into higher processor performance

Published in:

TENCON 2006. 2006 IEEE Region 10 Conference

Date of Conference:

14-17 Nov. 2006