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Architecture of a Wavelet Packet Transform Using Parallel Filters

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2 Author(s)
Farahani, M.A. ; Electr. & Comput. Eng. Fac. ; Eshghi, M.

In this paper, based on the word-serial pipeline architecture and parallel filter processing, a new architecture for direct and inverse wavelet packet transforms is introduced. This architecture increases the speed of the wavelet packet transforms. In this design, a word-serial architecture able to compute a complete wavelet packet transform (WPT) binary tree in an on-line fashion, and easily configurable in order to compute any required WPT sub tree is proposed. In this architecture, a high-pass filter and a low-pass filter are used concurrently, in order to compute the new coefficients. This architecture is suitable for the high speed on-line applications. With this architecture, the speed of the wavelet packet transforms is increased with a factor two, but the occupied area of the circuit is less than double. This architecture can be applied to any levels tree structure with any filter coefficients length

Published in:

TENCON 2006. 2006 IEEE Region 10 Conference

Date of Conference:

14-17 Nov. 2006

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