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Static Energy Reduction in Cache Memories Using Data Compression

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2 Author(s)
Kiyofumi Tanaka ; School of Information Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi-city, Ishikawa, 923¿1292 Japan. kiyofumi@jaist.ac.jp ; Aiko Matsuda

Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory. However, the energy consumption in the cache memory would approach or exceed 50% of the total consumption by the processor, which leads to a serious problem in terms of allowable temperature and high-speed processing. In the near future, static (leakage) energy will dominate the energy consumption in deep sub-micron processes. In this paper, we propose cache memory architecture that exploits gated-Vdd control per cache block and a dynamic data compression scheme in the secondary cache, and achieves efficient reduction of static energy consumed by the secondary cache memory. In the simulation, our technique reduced about 48% of leakage energy in the cache at maximum, and about 20% on average

Published in:

TENCON 2006 - 2006 IEEE Region 10 Conference

Date of Conference:

14-17 Nov. 2006