By Topic

Static Energy Reduction in Cache Memories Using Data Compression

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kiyofumi Tanaka ; School of Information Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi-city, Ishikawa, 923¿1292 Japan. ; Aiko Matsuda

Cache memory is effective in bridging a growing speed gap between a processor and relatively slow external main memory. However, the energy consumption in the cache memory would approach or exceed 50% of the total consumption by the processor, which leads to a serious problem in terms of allowable temperature and high-speed processing. In the near future, static (leakage) energy will dominate the energy consumption in deep sub-micron processes. In this paper, we propose cache memory architecture that exploits gated-Vdd control per cache block and a dynamic data compression scheme in the secondary cache, and achieves efficient reduction of static energy consumed by the secondary cache memory. In the simulation, our technique reduced about 48% of leakage energy in the cache at maximum, and about 20% on average

Published in:

TENCON 2006 - 2006 IEEE Region 10 Conference

Date of Conference:

14-17 Nov. 2006