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FPGA-Based High Area Efficient Time-To-Digital IP Design

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4 Author(s)
Min-Chuan Lin ; Dept. of Electron. Eng., Kun-Shan Univ. ; Tsai, Guo-Ruey ; Chun-Yi Liu ; Shi-Shien Chu

This paper proposes a novel design for a highly area efficient FPGA-based TDC (time to digital converter) IP (intelligent property) with resolution less than 30 ps. To avoid the unpredictable internal place and route (P&R) delay, a modified ring oscillator is presented. By integrating the gates delay and P&R delay, a design by combining schematic and VHDL codes, can generate a predictable and stable TDC module built in a Xilinx FPGA

Published in:

TENCON 2006. 2006 IEEE Region 10 Conference

Date of Conference:

14-17 Nov. 2006