FPGA-Based High Area Efficient Time-To-Digital IP Design

This paper proposes a novel design for a highly area efficient FPGA-based TDC (time to digital converter) IP (intelligent property) with resolution less than 30 ps. To avoid the unpredictable internal place and route (P&R) delay, a modified ring oscillator is presented. By integrating the gates delay and P&R delay, a design by combining schematic and VHDL codes, can generate a predictable and stable TDC module built in a Xilinx FPGA