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A Pipelined Architecture for a 20-point PFA

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2 Author(s)
Aghaee, N. ; Dept. of Electr. Eng., Tarbiat Modares Univ., Tehran ; Eshghi, M.

This paper presents a continuous-I/O word-serial pipelined structure for a 20-point prime-factor FFT algorithm (PFA), called pipelined PFA (P-PFA). The 20-point DFT is broken down into the 4-point and the 5-point partial DFTs, using the PFA. The 4-point and the 5-point partial DFTs are implemented using the 4-point butterfly and the 5-point Winograd Fourier transform algorithm (WFTA), respectively. The P-PFA includes three register units in addition to three shuffling units in the input, middle, and output. The register and the shuffling units arrange the data according to the Chinese remainder theorem mapping, the Good's mapping, and the natural order. The average signal to error ratio of the proposed P-PFA is between 30 and 35 dB, for 9-bit word length. The speed up of the P-PFA is about 1.2, for 9-bit word length. The area is about 40b+376 times the area of an adder, where b is the word length

Published in:

TENCON 2006. 2006 IEEE Region 10 Conference

Date of Conference:

14-17 Nov. 2006

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