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Reconfigurable Parallel VLSI Co-Processor for Space Robot Using FPGA

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5 Author(s)
Wei, R. ; Robot Res. Inst., Harbin Inst. of Technol. (HIT), Harbin ; Jin, M.H. ; Xia, J.J. ; Xie, Z.W.
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This paper proposes hardware solutions to the computation for the trigonometric and square root functions of inverse kinematics. They are based on an existing pipeline arithmetic which employs the CORDIC(Coordinate Rotation Digital Computer) algorithm. This integrated approach enhances computational efficiency by reducing the duplicate calculations of this functions and maximizing the parallel/pipelining processing for real-time robot control. The reliability of an onboard computer for space robot mostly depends on the reliability of the memory module. According to the fault mode in aerospace, the reconfigurable EDAC (Error Detect and Correct) system including Hamming coding and TMR(Triple Modular Redundancy) function on a FPGA (Field Programmable Gate Array) is implemented. The chip also implements peripheral controller such as AD interface and power control module. The whole system can be implemented in a single chip and the hardware system is more flexible and compact. Characteristics and performance analysis of the architecture are discussed through experiments.

Published in:

Robotics and Biomimetics, 2006. ROBIO '06. IEEE International Conference on

Date of Conference:

17-20 Dec. 2006