Referenced Items are not available for this document.
A high-speed CMOS phase/frequency detector (PFD) for faster frequency acquisition is presented. An improved CMOS D-type master-slave flip-flop is described and adopted. Higher speed is attributed to the reduced node capacitances. Charge-sharing phenomena are circumvented. An input delay scheme is employed to achieve faster acquisition. The optimal delay for PFD maximum operating frequency is analytically studied and a design guide is given.
Published in:
Consumer Electronics, IEEE Transactions on
(Volume:53
,
Issue:
1
)
Date of Publication: February 2007
- Page(s):
- 23 - 26
- ISSN :
- 0098-3063
- INSPEC Accession Number:
- 9392429
- Digital Object Identifier :
- 10.1109/TCE.2007.339496
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 02 April 2007
- Issue Date :
- February 2007
- Sponsored by :
- IEEE Consumer Electronics Society
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