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Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders

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6 Author(s)
G. Minana ; Comput. Archit. & Autom. Dept. of Complutense, Univ. of Madrid ; J. I. Hidalgo ; J. Lanchares ; J. M. Colmenar
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A hardware technique to reduce static and dynamic power consumption in functional units of 64-bit high-performance processors is presented here. The instructions that require an adder have been studied it can be concluded and that, there is a large percentage of instruction where one of the two source operands is always narrow and does not require a 64-bit adder. Furthermore, by analysing the executed applications, it is feasible to classify their internal operations according to their bit-width requirements and select the appropriate adder type that each instruction requires. This approach is based on substituting some of the 64-bit power-hungry adders with 32-bit ones, which consume much lower power, and modifying the protocol to issue as much instructions as possible to these low power consumption units, while incurring in negligible performance penalties. Five different configurations were tested for the execution units. Results indicate that this technique can save between up to 50% of the power consumed by the adders and up to 21% of the overall power consumption in the execution unit of high-performance architectures. Moreover, the simulations show good results in terms of power efficiency (IPC/W) and it can be affirmed that it could prevent the creation of hot spots in the functional units

Published in:

IET Computers & Digital Techniques  (Volume:1 ,  Issue: 2 )